Enhanced Debugging Solutions
Debugging issues found during post silicon validation is challenging. There is limited visibility into the internals of the chip. Standalone protocol-specific box instruments each have their own API and capabilities for programming stimulus and debugging responses from the chip. Generating appropriate stimulus and response data at the chip interfaces to isolate the problem in a repeatable way is very time consuming. Then there is debugging of the tests themselves to insure they work within the specified functionality of the IC.
The Test IP-based Post Silicon Validation system solves many of the functional debugging problems by having an integrated advanced test creation & debugging environment, using PSVM™ and supporting industry standard debugging tools like Synopsys Protocol Analyzer™ and Verdi-3™, and CPU core debuggers like Lauterbach™. Even with these tools and repeatable tests, there are times when visibility into the internal logic interactions of the chip is required to debug the problem.
In pre-silicon verification, hardware-based emulation is used to enable a significant speedup over software-based simulation. Emulation enables long IC subsystem test cases or full-chip SoC OS boot tests, for example, to be run prior to chip tape-out. Emulators also allow cycle-by-cycle visibility of chip internal logic during these accelerated simulations.
If emulation is part of your current pre-silicon toolkit, debugging tricky post-silicon issues on an emulator is highly desirable. The problem is that standalone protocol boxes and lab software doesn’t port back to emulation. This means it’s difficult if not impossible in some cases to bring a repeatable functional test case from post-silicon back to pre-silicon. What if it were possible to seamlessly bring post-silicon test cases back to emulation for debug without developing an expensive ad-hoc process?
With the TIP-based PSV system, and it’s powerful PSVM™-based development environment, post-silicon issues can be found, isolated with a streamlined test, and run on emulation using the same environment as in pre-silicon. Currently supported on the Synopsys ZeBu™ emulator with Emulation Test IP (eTIP), the same test that fails in post-silicon can be run without changes using PSVM™ and the failing random seed. Debugging on ZeBu™ uses Protocol Analyzer™ and Verdi-3™ just as in post-silicon!
Now, if the continuum from post-silicon back to pre-silicon emulation is available, so is the ability to write post-silicon tests on the emulation platform prior to first silicon . This not only allows the same tests to be run against the real chip without modification, but also provides a “shift left” by allowing earlier post-silicon test suite creation, shortening the overall silicon development cycle time.
Prototyping enables an interface or a small subsystem of a bigger SoC to be fitted into one or more FPGAs, allowing faster verification of the targeted logic. Prototyping systems generally run faster than emulators, but have less capacity and less seamless support from simulation. They have proved to be good for software driver debug of individual protocol interfaces of an SoC, and even subsystems. Because of these benefits, they are also used for early post-silicon test suite development.
Prototyping systems can run at the targeted SoC clock rate or a reduced rate, and can include SERDES PHYs or pre-PHY parallel interfaces. Connecting the TIP-based PSV system to the prototyping system allows protocol or subsystem-focused tests to be developed and run in pre-silicon. With minimal modification, these same tests can also run in post-silicon. This means that bare-metal software drivers can be debugged in pre-silicon at full speed! And individual protocol interface tests can be developed ahead of real silicon. Using
The TIP-based PSV development system currently supports Synopsys HAPS™, integrating with PSVM™ and the Synopsys pre-silicon development continuum.
Read more about the PSVM Emulation Framework.