Post Silicon Validation Solutions

Post silicon validation (PSV) of first silicon tends to be an ad hoc process, stitching together protocol testers from various manufacturers to create test cases and debug issues. While IC’s are getting to market, the process is far from ideal. Leveraging the tools and methodology of pre-silicon verification into post silicon validation is a key enabler to higher productivity. Test IP-based PSV is a paradigm shift from the way post silicon validation is currently done. Individual protocol testers, scopes, miscellaneous equipment from various vendors, and on-chip logic are cobbled together in an attempt to create meaningful stimulus, response checking, and debugging.
The problems with these ad hoc solutions:

  • Protocol boxes from multiple vendors generally do not work together well.  Each has its own driver software, programming model and debugging tools.
  • Tool flows from pre-silicon to post-silicon to production and back are nonexistent. This makes writing tests challenging and thus generally limited in robustness. Also, debugging suspected problems is difficult across more than one interface.

Test IP-based PSV

Benefits vs Single Protocol Box

One platform, multiple protocols
  • Same look and feel
    • Software, Graphical Debugger
  • Reduced learning curve
Same hardware platform.  Only TIP protocols change
  • Hardware and instrument purchases are decoupled
  • Save $
User-defined functionality
  • Allows for complex and robust testing
Highly programmable
  • Fast test creation, including random data, sequences and configurations
  • Easily modify for characterization and bug isolation
Partnering with Synopsys can deliver protocols quickly
  • Will be ready to engage during prototype phase

Test IP-based PSV

Benefits vs Multiple Protocol Boxes

Easily expand to subsystem and system testing
  • Leverage testbench and tests from interface to subsystem to SoC
    • PSVM modeled after UVM for intuitive pre-silicon leverage
Integrated multi-protocol features
  • Simple coordination of multiple protocols to create complex random tests
  • Graphical debugger integrated across all protocols for faster bug isolation
Partnering with Synopsys,deploying EDA tool chain
  • Seamless transition back to emulation for detailed corner case debugging
  • Verdi best-in-class graphical debugger with protocol view
  • Functional coverage via UCDB

No integrated platform has been available that supports the testing and debugging of both single and multiple protocols.  This post silicon validation capability is important because there are just not enough simulation or emulation cycles available to test everything in pre-silicon. The Test IP-based PSV system is specifically targeted at functional testing and problem characterization, as this is where the biggest holes exist in PSV today:

  • Fringe functionality & error cases
  • Power domain & distribution correctness
  • Power management controller functionality
  • Performance validation
  • Use case testing

The TIP-based PSV system has fully integrated stimulus generation, response checking, and debug features available across interface protocols – something which was previously found only in the pre-silicon world. It also includes a high level programming environment, PSVM™, which is similar to UVM™, allowing quick creation of complex test cases that are portable between pre-silicon and post-silicon.

Post Silicon Validation System Overview

  • Configurable with multiple Instances of Test IP
  • Multi-TIP synchronization & triggering
  • Real time, at-speed multi-protocol subsystem and system level test
  • Algorithmic stimulus generation & response checking
  • Trace memory and error trapping
  • Based on PCIe industry standard hardware
  • Supports FMC or HAPS compatible PHY daughter cards
  • PSVM Development Environment [pic]
  • Compatible with Synopsys Verdi Protocol Analyzer [pic]


System Features

Concurrent Test Requirement

TIP Test System Feature

Pre- to Post-Silicon Leverage
  • Same methodology and tools as pre-silicon
  • Use models allow extending the Pre-Si <–> Post-Si continuum
Deterministic operation, Repeatable test cases
  • TIP synchronization methods analogous to pre-silicon
  • Seed-based algorithmic stimulus
Back door access
  • Pre-load stimulus and response
  • Pre-load memory TIP (e.g. Flash)
Self-checking tests
  • Scoreboard methodology
  • Algorithmic response checking
  • Pre-loaded expect data with self-checking
Debug Hooks
  • View stimulus and response from DUT via Verdi Protocol Analyzer across all interfaces
  • Timestamped scoreboard data
  • Portable to pre-silicon emulation or FPGA platform for internal DUT debug visibility
Clock, Voltage Flexibility
  • Part of the TIP Carrier hardware, controlled by TIP API
Error Injection
  • Scenario-based callbacks in transaction processing flow for each TIP type
  • Pre-defined error injection mechanisms
Full Protocol Functionality and Coverage
  • Each TIP type is protocol compliant, and has a configuration object for per-test setup
  • Functional coverage support

Part of the tools and methodology from pre-silicon are emulation and FPGA prototyping — like Synopsys ZeBu and HAPS — which are in wide use for speeding up simulation and getting more cycles prior to 1st silicon. Our TIP-based PSV system provides a seamless link back to emulation and FPGA prototyping.  This allows failing tests to be replayed and debugged in the pre-silicon environment, as well as promoting early “head start” PSV test development in the pre-silicon environment.

Creating this seamless continuum gives users of the TIP-based PSV system a consistent flow by leveraging tests, methodologies, and tools across both phases of IC development. This provides opportunities for not only a “shift left” of development, but also improvements in IC development cycle time and ultimately time-to-market/revenue.