Portable Stimulus Validation Methodology


PSVM™ is an efficient, directed random, repeatable and self checking validation methodology that allows test portability between pre-silicon and post-silicon platforms. It unites all commonly used pre-silicon verification techniques and idioms with the post silicon validation field:

  • UVM “like” class structure and flow
  • Constrained/Directed random test cases
  • Highly repeatable test cases (seed & time based)
  • Robust event synchronization method for creating complex test cases
  • Fully self-checking and regressable test suites
  • Standardized logging and error reporting
  • Debug of failing tests (transaction flow & waveforms) using 3rd party GUI debuggers like Synopsys Verdi / Protocol Analyzer
  • Hierarchical approach allowing integration of interface and sub-system tests into system level
  • Integration of 3rd party instruments (e.g. Lauterbach debugger, DC measurement)
  • Well documented APIs and examples

Using PSVM™ a validation team can efficiently create, integrate and reuse, complex directed random SoC scenarios.  PSVM™ works in Virtual Prototyping environments (like Synopsys Virtualizer), emulation and FPGA prototyping (like Synopsys ZeBu and HAPS, respectively), and in the post-silicon lab.  Each test developed with Test Evolution technology and PSVM™ is portable across development and test platforms from pre-silicon to post-silicon!

This powerful set of portable stimulus technology allows complete test portability for software-driven verification and use-case tests that can span platforms, leveraging content across SoC development teams, and saving both overall effort and schedule time.  Both critical for success with today’s short and intense SoC development timelines, and huge penalties for being late to market!