Virtual Prototyping Solutions

The integration of increasingly complex hardware and software is a significant challenge for semiconductor and OEM companies developing next-generation wireless, consumer and automotive devices. Traditional methods of serialized hardware and software development–where the vast majority of software is developed and verified after the silicon design is complete–often fail to meet aggressive product development schedules.

Virtual prototyping results in faster time-to-market through earlier and faster software development and improved communication throughout the development chain. Software engineers are able to start development months before the hardware design is complete, enabling full system bring-up to occur within days of silicon availability.

Software driven verification, where product groups can specify use cases based on product requirements, and then work with hardware and software groups to run tests specific to device operating modes, is an elusive goal.  There is  agreement within the industry that this is the direction hardware and software validation must go to keep up with the complexities of current and future products. But there has been no robust solution that allows portability of use case tests across platforms.  Until now!

Test Evolution has created Virtual Prototyping Test IP, or vpTIP, which are TLM models that plug into a virtual prototyping platform.  They have the same behavior and user API as eTIP and TIP for a specific interface protocol, and run at the speed of a virtual prototype.

Combining PSVM™ with Synopsys Virtualizer, and bringing with them vpTIP for various industry standard protocols, Test Evolution and Synopsys can extend the benefits of virtual prototyping to software driven / use case validation all the way to the SoC pins.

Extending Test IP’s capabilities for seed-based repeatable stimulus and response checking, and functional coverage to vpTIP enables the following:

  • Development of orthogonal use case tests that can be independently created and debugged, using “directed random” stimulus and response checking to “randomize around the edges” of the use case.
  • Combinations of orthogonal use cases, with coordination and randomization within PSVM™ to build highly effective tests that stress the software drivers and OS platform .
  • Portability of the use case test suite to emulation or FPGA prototyping for testing with real hardware blocks and subsystems.
  • Portability of the use case test suite to post-silicon, and “taking the brakes off” to allow the test suites to run for hours or days of real time execution and self-checking.

The above are not possible with current tools and methods!

PCIe Gen3.1 vpTIP is currently in early development with a lead customer.