There are four major roadblocks in post-silicon validation and test for today’s SoCs:
- Manually written directed tests using low level instrument-specific APIs do not scale to support SoC validation.
- Protocol analyzers & testers validate a single interface but cannot support subsystem/system level function use case test .
- Validation setups are custom, ad-hoc solutions that are incompatible with pre-silicon or production test
- Production ATE architectures are overkill for structural test and unable to economically address at-speed functional test.
Test Evolution has developed a platform based on patented Test IP technology that enables the advances in pre-silicon methodologies to be leveraged into post-silicon validation and test.
This new approach leverages FPGA technology and low cost industry standards based systems to provide solutions that scale from single IP core validation to subsystem/system level functional validation to at-speed production test.
And most importantly this approach uses TIP to extend the overall device continuum from pre-silicon through post-silicon validation and production test.
Common Test Development Environment – read more
- Multi-protocol test creation and debugging
- PSVM (Portable Stimulus Validation Method)
- Leverage TIP-based test across the entire continuum
Virtual Prototyping TIP (vpTIP) – read more
- Use case test creation through interface pins
Emulator TIP (eTIP) – read more
- Faster performance than standard emulation transactors
Post Silicon Validation (TIP) – read more
- Real-time operation across interface
Semiconductor Test (TIP) – read more
- Uses the same TIP architecture as post-silicon validation
- Add structural test coverage (scan, BIST) to the test list
- Streamline the TIP-based functional test list to optimize production test time
- Transparent support of multi-site testing to improve throughput